industrial temperature range IDT74AUC32373 1.8v cmos 32-bit transparent d-type latch with 3-state outputs 1 october 2003 IDT74AUC32373 industrial temperature range 1.8v cmos 32-bit transparent d-type latch with 3-state outputs description: this 32-bit transparent d-type latch is built using advanced cmos technol- ogy. the device can be used as a single 32-bit latch, as two 16-bit latches, or as four 8-bit latches. when the latch enable (le) input is high, the q outputs follow the data (d) inputs. when le is taken low, the q outputs are latched at the levels set up at the d inputs. a buffered output enable ( oe ) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the oe input does not affect the internal operation of the latch. this device is fully specified for partial power-down applications using i off . the i off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. to ensure the high-impedance state during power up or power down, oe should be tied to v dd through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. the idt logo is a registered trademark of integrated device technology, inc. ? 2003 integrated device technology, inc. dsc-6375/2 features: ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ? 1.8v optimized ? 0.8v to 2.7v operating range ? inputs/outputs tolerant up to 3.6v ? output drivers: 8ma @ 1.8v ? supports hot insertion ? available in 96-ball lfbga package functional block diagram applications: ? high performance, low voltage communications systems ? high performance, low voltage computing systems 2 oe 2 le 2 d 1 2 q 1 h3 h4 e5 e2 4 oe 4 le 4 d 1 4 q 1 t3 t4 n5 n2 1 oe d c 1 le d 1 1 q 1 to seven other channels 3 oe 3 le 3 d 1 3 q 1 j3 j4 j5 j2 a3 a4 a5 a2 c 1 1 d c 1 1 d to seven other channels to seven other channels to seven other channels c 1 1 d c 1 1 d
industrial temperature range 2 IDT74AUC32373 1.8v cmos 32-bit transparent d-type latch with 3-state outputs pinout configuration 1.5mm max. 1.4mm nom. 1.3mm min. 0.8mm 6 5 4 3 2 1 top view abcdefghjklmnprt abcdefghjklmnprt 6 5 4 3 2 1 13.5mm 5.5mm ab c e f g h j k l m np d t r 6 5 4 3 2 1 1 d 6 1 d 8 2 d 1 2 d 22 d 4 2 d 8 2 oe 1 d 4 1 d 5 1 d 7 2 d 6 2 d 7 2 d 3 2 d 5 1 d 2 1 d 3 1 d 1 gnd gnd 3 d 8 3 d 2 3 d 4 4 d 1 4 d 3 4 d 2 3 d 3 3 d 5 4 d 4 3 d 1 4 d 6 gnd gnd 1 q 1 v cc gnd v cc 1 q 2 1 q 3 4 q 6 4 q 8 gnd gnd 2 q 2 2 q 4 1 q 4 1 q 51 q 7 2 q 6 2 q 7 3 q 7 4 q 2 3 q 3 3 q 5 4 q 4 3 q 1 1 q 6 1 q 8 2 q 1 2 q 8 2 q 3 2 q 5 3 q 6 3 q 8 3 q 2 3 q 4 4 q 1 4 q 3 gnd v cc gnd v cc gnd gnd v cc gnd gnd v cc gnd v cc 3 d 7 3 d 6 1 oe 2 le 1 le 3 le 4 d 54 d 8 4 d 7 4 oe 4 q 7 4 q 5 v cc gnd 4 le gnd 3 oe 96 ball lfbga package attributes lfbga top view
industrial temperature range IDT74AUC32373 1.8v cmos 32-bit transparent d-type latch with 3-state outputs 3 symbol parameter conditions typ. max. unit c in (1) input capacitance v in = 0v 3 4 pf c out (2) output capacitance v out = 0v 5.5 6.5 pf c i (3) input port capacitance v in = 0v 3 4 pf capacitance (t a = +25c, f = 1.0mhz, v dd = 2.5v) notes: 1. applies to control inputs. 2. applies to data outputs. 3. applies to data inputs. symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +3.6 v (all input and v dd terminals) v term terminal voltage with respect to gnd ?0.5 to +3.6 v (any i/o or output terminals in high- impedance or power-off state) t stg storage temperature ?65 to +150 c i out continuous dc output current 20 ma i ik continuous clamp current, 50 ma v i < 0, or v i > v dd i ok continuous clamp current, v o < 0 ?50 ma i dd continuous current through 100 ma i ss each v dd or gnd absolute maximum ratings (1) (1) (1) (1) (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. function table (each 8-bit latch) (1) notes: 1. h = high voltage level l = low voltage level x = don't care z = high-impedance 2. level of q before the indicated steady-state conditions were established. inputs output x oe xle xdx xqx lhh h lhl l llx q (2) hxx z pin description pin names description x d x data inputs xle latch enable inputs x q x 3-state outputs x oe 3-state output enable inputs (active low)
industrial temperature range 4 IDT74AUC32373 1.8v cmos 32-bit transparent d-type latch with 3-state outputs symbol parameter test conditions min. max. unit v dd supply voltage 0.8 2.7 v v dd = 0.8v v dd ? v dd = 1.1v to 1.3v 0.65 x v dd ? v ih input high voltage level v dd = 1.4v to 1.6v 0.65 x v dd ?v v dd = 1.65v to 1.95v 0.65 x v dd ? v dd = 2.3v to 2.7v 1.7 ? v dd = 0.8v ? 0 v dd = 1.1v to 1.3v ? 0.35 x v dd v il input low voltage level v dd = 1.4v to 1.6v ? 0.35 x v dd v v dd = 1.65v to 1.95v ? 0.35 x v dd v dd = 2.3v to 2.7v ? 0.7 v i input voltage 0 2.7 v v o output voltage active state 0 v dd v 3-state 0 2.7 v dd = 0.8v ? ?0.7 v dd = 1.1v ? ?3 i oh high level output current v dd = 1.4v ? ?5 ma v dd = 1.65v ? ?8 v dd = 2.3v ? ?9 v dd = 0.8v ? 0.7 v dd = 1.1v ? 3 i ol low level output current v dd = 1.4v ? 5 ma v dd = 1.65v ? 8 v dd = 2.3v ? 9 ? t/ ? v input transition rise or fall time ? 20 ns/v t a operating free-air temperature ?40 +85 c recommended operating characteristics (1) note: 1. all unused inputs of the device must be held at v dd or gnd to ensure proper operation. symbol parameter test conditions min. typ. max. unit i ih input high or low current v dd = 2.7v, v i = v dd or gnd ? ? 5 a i il all inputs i off input/output power off leakage v dd = 0v, v in or v o 2.7v ? ? 10 a i ozh high impedance output current v dd = 2.7v v o = v dd ? ? 10 a i ozl (3-state output pins) v o = gnd ? ? 10 i ddl quiescent power supply current v dd = 0.8v to 2.7v ? ? 40 a i ddh v in = gnd or v dd i ddz dc electrical characteristics over operating range (1) following conditions apply unless otherwise specified: operating conditions: t a = ?40c to +85c note: 1. all unused inputs of the device must be held at v dd or gnd to ensure proper operation.
industrial temperature range IDT74AUC32373 1.8v cmos 32-bit transparent d-type latch with 3-state outputs 5 symbol parameter test conditions (1) min. typ. max. unit v oh output high voltage v dd = 0.8v - 2.7v i oh = ?100 av dd - 0.1 ? ? v dd = 0.8v i oh = ?0.7ma ? 0.55 ? v dd = 1.1v (2) i oh = ?3ma 0.8 ? ? v v dd = 1.4v (3) i oh = ?5ma 1 ? ? v dd = 1.65v (4) i oh = ?8ma 1.2 ? ? v dd = 2.3v (5) i oh = ?9ma 1.8 ? ? v ol output low voltage v dd = 0.8v - 2.7v i oh = 100 a ? ? 0.2 v dd = 0.8v i ol = 0.7ma ? 0.25 ? v dd = 1.1v (2) i ol = 3ma ? ? 0.3 v v dd = 1.4v (3) i ol = 5ma ? ? 0.4 v dd = 1.65v (4) i ol = 8ma ? ? 0.45 v dd = 2.3v (5) i oh = 9ma ? ? 0.6 output drive characteristics notes: 1. v il and v ih must be within the min. or max. range shown in the dc electrical characteristics table for the appropriate v dd range. t a = -40c to +85c. 2. demonstrates operation for nominal v dd = 1.2v. 3. demonstrates operation for nominal v dd = 1.5v. 4. demonstrates operation for nominal v dd = 1.8v. 5. demonstrates operation for nominal v dd = 2.5v. switching characteristics (1) note: 1. see test circuits and waveforms. t a = -40c to +85c. v dd = 0.8v v dd = 1.2v0.1v v dd = 1.5v0.1v v dd = 1.8v0.15v v dd = 2.5v0.2v symbol parameter typ. min. max. min. max. min. typ. max. min. max. unit t plh propagation delay xdx to xqx 8 1.1 3.8 0.6 2.4 0.7 1.5 2.4 0.6 1.9 ns t phl xle to xqx 10.6 1.4 4.9 0.7 3.2 0.7 1.6 2.8 0.6 2.1 t pzh output enable time 9 1.3 4.5 0.6 2.9 0.8 1.7 2.9 0.7 2.2 ns t pzl x oe to xqx t phz output disable time 13 2.4 7 2.4 4.8 1.1 2.7 4.6 0.4 2.5 ns t plz x oe to xqx t su set-up time, data before le 1.7 0.9 ? 0.4 ? 0.4 ? ? 0.4 ? ns t h hold time, data after le ? 0.9 ? 0.4 ? 0.4 ? ? 0.4 ? ns t w pulse duration, le high 4.2 2.9 ? 2.3 ? 2.1 ? ? 1.7 ? ns operating characteristics, t a = 25c symbol parameter test conditions v dd = 0.8v v dd = 1.2v v dd = 1.5v v dd = 1.8v v dd = 2.5v unit c pd power dissipation capacitance c l = 0pf 21 22 23 25 29 pf per output, outputs enabled f = 10mhz c pd power dissipation capacitance 5 5 6 7 10 pf per output, outputs disabled
industrial temperature range 6 IDT74AUC32373 1.8v cmos 32-bit transparent d-type latch with 3-state outputs open v load gnd v dd pulse generator d.u.t. r l c l r t v in v out (1) same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v dd v t v t v dd v t control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v ol + v lz v oh v t v t t pzl v load/2 v load/2 v dd v t v ol v oh - v hz r l timing input data input t su t h v t v dd 0v 0v v dd v t v t low-high-low pulse high-low-high pulse 0v v dd v t v t t w test circuits and waveforms propagation delay test circuits for all outputs enable and disable times note: 1. diagram shown for input control enable-low and input control disable-high. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. note: 1. pulse generator for all pulses: rate 10mhz; slew rate 1v/ns. test switch open drain disable low v load enable low disable high gnd enable high all other tests open switch position setup and hold times test conditions (1) symbol v dd = 0.8v v dd = 1.2v0.1v v dd = 1.5v0.1v v dd = 1.8v0.15v v dd = 2.5v0.2v unit v load 2xv dd 2xv dd 2xv dd 2xv dd 2xv dd v v t v dd /2 v dd /2 v dd /2 v dd /2 v dd /2 v v lz 100 100 100 150 150 mv v hz 100 100 100 150 150 mv r l 2 2 2 1 0.5 k ? c l 15 15 15 30 30 pf pulse width
industrial temperature range IDT74AUC32373 1.8v cmos 32-bit transparent d-type latch with 3-state outputs 7 ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx auc xxx xx package device type temp. range bf 32 74 low-profile fine pitch ball grid array 32-bit transparent d-type latch with 3-state outputs ? 40c to +85c xx family 373 32-bit bus density x bus- hold blank no bus-hold x temp. i industrial temperature range
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